The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of high-K dielectric layers in semiconductor devices.
Fabrication of semiconductor devices, such as a metal-oxide-semiconductor (MOS) integrated circuit, involves numerous processing steps. In a semiconductor device, a gate dielectric, typically formed from silicon dioxide (xe2x80x9coxidexe2x80x9d), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many present processes employ features, such as gate conductors and interconnects, which have less than 0.18 xcexcm critical dimension. As feature sizes continue to decrease, the size of the resulting transistor as well as the interconnect between transistors also decreases. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
As MOSFET feature sizes decrease, gate oxide thickness decreases as well. This decrease in gate oxide thickness is driven in part by the demands of overall device scaling. As gate conductor widths decrease, for example, other device dimensions must also decrease in order to maintain proper device operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts.
As a result of the continuing decrease in feature size, gate oxide thickness has been reduced so much that oxides are approaching thicknesses on the order of ten angstroms (xc3x85). Unfortunately, thin oxide films may break down when subjected to an electric field, particularly for gate oxides less than 50 xc3x85 thick. It is probable that even for a relatively low gate voltage of 3V, electrons can pass through such a thin gate oxide by a quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that some of these electrons may become entrapped within the gate oxide by, e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, the threshold voltage VT may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of gate voltage, as a result of defects in the gate oxide. Such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice.
A more promising approach to further increasing gate dielectric capacitance may be to increase the permittivity of the gate dielectric. Permittivity, xcex5, of a material reflects the ability of the material to be polarized by an electric field. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, xcex50. Hence, the relative permittivity, referred to as the dielectric constant, of a material is defined as:
k=xcex5/xcex50
While silicon dioxide (sometimes simply referred to as xe2x80x9coxidexe2x80x9d) has a dielectric constant of approximately 3.9, other materials have higher K values. Silicon nitride (xe2x80x9cnitridexe2x80x9d), for example, has a K of about 6 to 9 (depending on formation conditions). Much higher K values of, for example, 20 or more can be obtained with various transition metal oxides including tantalum oxide (Ta2O5), barium strontium titanate (xe2x80x9cBSTxe2x80x9d), and lead zirconate titanate (xe2x80x9cPZTxe2x80x9d). Using a high-K dielectric material for a gate dielectric would allow a high capacitance to be achieved even with a relatively thick dielectric layer. For example, a nitride gate dielectric with a K of 7.8 and a thickness of 100 angstroms is substantially electrically equivalent to an oxide gate dielectric (K about 3.9) having a thickness of about 50 angstroms. For even higher-K dielectric materials, even thicker gate dielectric layers could be formed while maintaining capacitance values higher than are possible with even very thin oxide layers. In this way, the reliability problems associated with very thin dielectric layers may be avoided while transistor performance is increased.
One problem which has been reported relating to integration of high-K dielectric materials is oxidation of silicon by certain high-K dielectric materials when the high-K dielectric material is formed directly on a silicon substrate. Since oxidation results in formation of what may be referred to as a xe2x80x9cstandard-Kxe2x80x9d dielectric material, some of the benefit of the high-K dielectric material is considered to be lost. In addition, reactions considered adverse between the high-K dielectric material and standard-K dielectric materials may also occur.
Thus, a method of forming a relatively high-K dielectric material which either overcomes or takes advantage of such reactions, and which provides the electrical advantages of a higher K is needed.
The present invention relates to a method of making a semiconductor device having a composite dielectric layer, including the steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, wherein one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.
The present invention further relates to a semiconductor device having a composite dielectric layer, including a semiconductor substrate; alternating sub-layers of a first dielectric material and a second dielectric material on the semiconductor substrate, the sub-layers forming a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, wherein one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material; and the composite dielectric layer includes a reaction product of the high-K dielectric material and the standard-K dielectric material.
Thus, the present invention overcomes the problem of forming a high-K dielectric material which overcomes and takes advantage of previously disfavored reactions between dielectric materials, to form a composite dielectric layer which includes a reaction product of the high-K dielectric material and the standard-K dielectric material, which is obtained by annealing a layered dielectric structure at an elevated temperature.